| [1] | Agathe Herrou, Florent de Dinechin, Stéphane Letz, Yann Orlarey, and Anastasia Volkova. Towards Fixed-Point Formats Determination for Faust Programs. In Journées d'Informatique Musicale 2024, Marseille, France, May 2024. [ bib | http | .pdf ] |
| [2] | Lucas Chaloyard, Florent de Dinechin, Marie-Pierre Escudié, and Lionel Morel. Bare minimal computer for everyone. In Undone Computer Science, February 2024. [ bib ] |
| [3] | Florent de Dinechin and Martin Kumm. Application-Specific Arithmetic. Springer, 2024. [ bib | http ] |
| [4] | Orégane Desrentes, Benoît Dupont de Dinechin, and Florent de Dinechin. Exact Fused Dot Product Add Operators. In International Symposium on Computer Arithmetic (ARITH). IEEE, September 2023. [ bib | http | .pdf ] |
| [5] | Maxime Popoff, Romain Michon, Tanguy Risset, Pierre Cochard, Stephane Letz, Yann Orlarey, and Florent de Dinechin. Audio DSP to FPGA Compilation. In International Conference on Application-specific Systems, Architectures and Processors (ASAP 2023), pages 31--33, Porto, Portugal, July 2023. IEEE. [ bib | DOI | http | .pdf ] |
| [6] | Anastasia Volkova, Rémi Garcia, Florent de Dinechin, and Martin Kumm. Hardware-optimal digital FIR filters: one ILP to rule them all and in faithfulness bind them. In Asilomar Conference on Signals, Systems, and Computers, February 2023. [ bib | http ] |
| [7] | Orégane Desrentes and Florent de Dinechin. Using integer linear programming for correctly rounded multipartite architectures. In International Conference on Field Programmable Technology, December 2022. [ bib | http | .pdf ] |
| [8] | Paolo Montuschi, Jean-Michel Muller, and Florent de Dinechin. Computer Arithmetic: Continuing a Long and Steady Emergence. Computer, 55(10):4--6, October 2022. [ bib | http ] |
| [9] | Andreas Böttcher, Martin Kumm, and Florent de Dinechin. Resource Optimal Squarers for FPGAs. In International Conference on Field-Programmable Logic and Applications (FPL). IEEE, August 2022. [ bib | DOI | http | .pdf ] |
| [10] | Luc Forget, Gauthier Harnisch, Ronan Keryell, and Florent de Dinechin. A single-source C++20 HLS flow for function evaluation on FPGA and beyond. In HEART 2022 - 12th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, June 2022. [ bib | http | .pdf ] |
| [11] | Maxime Christ, Luc Forget, and Florent de Dinechin. Lossless differential table compression for hardware function evaluation. IEEE Transactions on Circuits and Systems II: Express Briefs, 69(3):1642--1646, March 2022. [ bib | http | .pdf ] |
| [12] | Maxime Christ, Florent de Dinechin, and Frédéric Pétrot. Low-precision logarithmic arithmetic for neural network accelerators. In Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2022. [ bib | http | .pdf ] |
| [13] | Andreas Böttcher, Martin Kumm, and Florent de Dinechin. Resource optimal truncated multipliers for FPGAs. In 28th IEEE Symposium of Computer Arithmetic (ARITH-28), June 2021. [ bib | http | .pdf ] |
| [14] | Florent de Dinechin, Silviu Filip, Martin Kumm, and Anastasia Volkova. Towards arithmetic-centered filter design. In 28th IEEE Symposium of Computer Arithmetic (ARITH-28), June 2021. [ bib | http | .pdf ] |
| [15] | Luc Forget, Yohann Uguen, and Florent de Dinechin. Comparing posit and ieee-754 hardware cost. 2021. [ bib | http ] |
| [16] | Andre Guntoro, Cecilia De La Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, and Sangeeth Nambiar. Next generation arithmetic for edge computing. In Design, Automation & Test in Europe (DATE), pages 1357--1365. IEEE, 2020. [ bib ] |
| [17] | Yohann Uguen, Florent de Dinechin, Victor Lezaud, and Steven Derrien. Application-specific arithmetic in high-level synthesis tools. Transactions on Architecture and Code Optimization, 17(1), 2020. [ bib | .pdf ] |
| [18] | Andrea Bocco, Tiago Trevisan Jost, Albert Cohen, Florent de Dinechin, Yves Durand, and Christian Fabre. Byte-aware floating-point operations through a UNUM computing unit. In 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI SOC), October 2019. [ bib ] |
| [19] | Yohann Uguen, Luc Forget, and Florent de Dinechin. Evaluating the hardware cost of the posit number system. In 29th International Conference on Field-Programmable Logic and Applications (FPL), Barcelona, Spain, September 2019. [ bib | http | .pdf ] |
| [20] | Tiago Trevisan Jost, Andrea Bocco, Yves Durand, Christian Fabre, Florent de Dinechin, and Albert Cohen. Variable precision floating-point RISC-V coprocessor evaluation using lightweight software and compiler support. In Third Workshop on Computer Architecture Research with RISC-V (CARRV), June 2019. [ bib ] |
| [21] | Luc Forget, Yohann Uguen, Florent de Dinechin, and David Thomas. A type-safe arbitrary precision arithmetic portability layer for HLS tools. In HEART 2019 - International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, June 2019. [ bib | http | .pdf ] |
| [22] | Florent de Dinechin. Reflections on 10 years of FloPoCo. In 26th IEEE Symposium of Computer Arithmetic (ARITH-26), June 2019. [ bib | http | .pdf ] |
| [23] | Andrea Bocco, Yves Durand, and Florent de Dinechin. Dynamic precision numerics using a variable-precision UNUM type I HW coprocessor. In 26th IEEE Symposium of Computer Arithmetic (ARITH-26), June 2019. [ bib ] |
| [24] | Florent de Dinechin, Silviu-Ioan Filip, Luc Forget, and Martin Kumm. Table-based versus shift-and-add constant multipliers for FPGAs. In 26th IEEE Symposium of Computer Arithmetic (ARITH-26), June 2019. [ bib | http | .pdf ] |
| [25] | Anastasia Volkova, Matei Istoan, Florent de Dinechin, and Thibault Hilaire. Towards hardware IIR filters computing just right: Direct form I case study. IEEE Transactions on Computers, 68(4), April 2019. [ bib | http | .pdf ] |
| [26] | Florent de Dinechin, Luc Forget, Jean-Michel Muller, and Yohann Uguen. Posits: the good, the bad and the ugly. In Conference on Next-Generation Arithmetic, March 2019. [ bib | http ] |
| [27] | Andrea Bocco, Yves Durand, and Florent de Dinechin. SMURF: Scalar multiple-precision unum Risc-V floating-point accelerator for scientific computing. In Conference on Next-Generation Arithmetic, March 2019. [ bib | http ] |
| [28] | Florent de Dinechin, Maxime Darrin, Antonin Dudermel, Sébastien Michelland, and Alban Reynaud. Une architecture minimisant les échanges entre processeur et mémoire. In Conférence en parallélisme, architecture et système (COMPAS), July 2018. [ bib | http ] |
| [29] | Martin Kumm, Oscar Gustafsson, Florent de Dinechin, Johannes Kappauf, and Peter Zipf. Karatsuba with rectangular multipliers for FPGAs. In 25th IEEE Symposium of Computer Arithmetic (ARITH-25), June 2018. Best paper award. [ bib | .pdf ] |
| [30] | Jean-Michel Muller, Nicolas Brunie, Florent de Dinechin, Claude-Pierre Jeannerod, Mioara Joldes, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, and Serge Torres. Handbook of Floating-Point Arithmetic, 2nd edition. Birkhauser Boston, 2018. [ bib ] |
| [31] | Yohann Uguen, Florent de Dinechin, and Steven Derrien. Bridging High-Level Synthesis and Application-Specific Arithmetic: The Case Study of Floating-Point Summations. In 27th International Conference on Field-Programmable Logic and Applications (FPL). IEEE, September 2017. [ bib | http | .pdf ] |
| [32] | Andrea Bocco, Yves Durand, and Florent de Dinechin. Hardware support for UNUM floating point arithmetic. In 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), June 2017. [ bib ] |
| [33] | Yohann Uguen and Florent de Dinechin. Design-space exploration for the Kulisch accumulator. March 2017. [ bib | http | .pdf ] |
| [34] | Matei Istoan and Florent de Dinechin. Automating the pipeline of arithmetic datapaths. In DATE 2017, Lausanne, Switzerland, March 2017. [ bib | .pdf ] |
| [35] | H. Fatih Ugurdag, Florent de Dinechin, Y. Serhan Gener, Sezer Gören, and Laurent-Stéphane Didier. Hardware division by small integer constants. IEEE Transactions on Computers, 66(12):2097--2110, 2017. [ bib | http | .pdf ] |
| [36] | Matei Istoan and Florent de Dinechin. Pipeline automatique d'opérateurs dans flopoco 5.0. In COMPAS'2016: Conférence d'informatique en Parallélisme, Architecture et Système, July 2016. [ bib ] |
| [37] | Julien Le Maire, Nicolas Brunie, Florent de Dinechin, and Jean-Michel Muller. Computing floating-point logarithms with fixed-point operations. In 23rd Symposium of Computer Arithmetic, July 2016. [ bib | http | .pdf ] |
| [38] | Hatam Abdoli, Hooman Nikmehr, Naser Movahedinia, and Florent de Dinechin. Improving energy efficiency of OFDM using adaptive-precision reconfigurable FFT. Circuits, Systems, and Signal Processing, pages 1--25, 2016. [ bib | DOI ] |
| [39] | Yohann Uguen, Florent de Dinechin, and Steven Derrien. Optimisations arithmétiques en contexte pour la synthèse de haut niveau. Presented at COMPAS 2016, 2016. [ bib ] |
| [40] | Nicolas Brunie, Florent de Dinechin, Olga Kupriianova, and Christoph Lauter. Code generators for mathematical functions. In 22nd Symposium of Computer Arithmetic. IEEE, June 2015. Best paper award. [ bib | .pdf ] |
| [41] | Florent de Dinechin and Matei Istoan. Hardware implementations of fixed-point Atan2. In 22nd IEEE Symposium of Computer Arithmetic (ARITH-22), pages 34--41, June 2015. [ bib | .pdf ] |
| [42] | Florent de Dinechin and Jean-Michel Muller. Princeton Companion to Applied Mathematics, chapter Evaluating elementary functions. 2015. [ bib ] |
| [43] | Florent de Dinechin, Matei Istoan, and Abdelbassat Massouri. Sum-of-product architectures computing just right. In Application-Specific Systems, Architectures and Processors (ASAP). IEEE, 2014. [ bib | http | .pdf ] |
| [44] | Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, and Bogdan Popa. Arithmetic core generation using bit heaps. In Field-Programmable Logic and Applications, September 2013. [ bib | .pdf ] |
| [45] | Florent de Dinechin, Matei Istoan, and Guillaume Sergent. Fixed-point trigonometric functions on FPGAs. SIGARCH Computer Architecture News, 41(5):83--88, 2013. [ bib | .pdf ] |
| [46] | Florent de Dinechin, Christoph Lauter, Jean-Michel Muller, and Serge Torres. On Ziv's rounding test. ACM Transactions on Mathematical Software, 39(4), 2013. [ bib | http | .pdf ] |
| [47] | Nicolas Brunie, Florent de Dinechin, and Benoît de Dinechin. Conception d'une matrice reconfigurable pour coprocesseur fortement couplé. In Conférence en parallélisme, architecture et système (COMPAS), January 2013. [ bib | http ] |
| [48] | Nicolas Brunie, Florent de Dinechin, Matei Istoan, and Guillaume Sergent. L'arithmétique sur le tas. In Conférence en parallélisme, architecture et système (COMPAS), January 2013. [ bib | http ] |
| [49] | Florent de Dinechin and Bogdan Pasca. High-Performance Computing using FPGAs, chapter Reconfigurable Arithmetic for High Performance Computing, pages 631--664. Springer, 2013. [ bib | .pdf ] |
| [50] | Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, and Bogdan Pasca. Floating-point exponentiation units for reconfigurable computing. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 2013. [ bib | .pdf ] |
| [51] | Nicolas Brunie, Florent de Dinechin, and Benoît Dupont de Dinechin. Mixed-precision merged multiplication and addition operator. Patent WO/2012/175828, December 2012. [ bib ] |
| [52] | Eric Dutisseuil, Jean-Marc Tanguy, Adrian Voicila, Rémi Laube, Francois Bore, Honore Takeugming, Florent de Dinechin, Fréderic Cerou, and Gabriel Charlet. 34 Gb/s PDM-QPSK coherent receiver using SiGe ADCs and a single FPGA for digital signal processing. In Optical Fiber Communication, March 2012. [ bib ] |
| [53] | Florent de Dinechin and Laurent-Stéphane Didier. Table-based division by small integer constants. In Applied Reconfigurable Computing, pages 53--63, March 2012. [ bib | .pdf ] |
| [54] | Florent de Dinechin. Multiplication by rational constants. IEEE Transactions on Circuits and Systems, II, 52(2):98--102, February 2012. [ bib | .pdf ] |
| [55] | Florent de Dinechin. The arithmetic operators you will never see in a microprocessor. In 20th Symposium on Computer Arithmetic, pages pp 189--190. IEEE, July 2011. [ bib | .pdf ] |
| [56] | Florent de Dinechin and Bogdan Pasca. Designing custom arithmetic data paths with FloPoCo. IEEE Design & Test of Computers, 28(4):18--27, July 2011. [ bib | .pdf ] |
| [57] | Florent de Dinechin, Christoph Lauter, and Guillaume Melquiond. Certifying the floating-point implementation of an elementary function using Gappa. IEEE Transactions on Computers, 60(2):242--253, February 2011. [ bib | DOI | http | .pdf ] |
| [58] | Nicolas Brunie, Florent de Dinechin, and Benoît Dupont de Dinechin. A mixed-precision fused multiply and add. In 45th Asilomar Conference on Signals, Systems & Computers, 2011. [ bib | .pdf ] |
| [59] | Florent de Dinechin, Jean-Michel Muller, Bogdan Pasca, and Alexandru Plesco. An FPGA architecture for solving the Table Maker's Dilemma. In Application-Specific Systems, Architectures and Processors (ASAP), pages 187--194, Santa Monica, United States, 2011. IEEE. Best paper award. [ bib | DOI | .pdf ] |
| [60] | Florent de Dinechin and Bogdan Pasca. Floating-point exponential functions for DSP-enabled FPGAs. In Field Programmable Technologies, pages 110--117, December 2010. [ bib | .pdf ] |
| [61] | Alvaro Vazquez and Florent de Dinechin. Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs. In Field-Programmable Technology, pages 126--133, December 2010. [ bib | .pdf ] |
| [62] | Vincent LefХvre, Philippe ThИveny, Florent de Dinechin, Claude-Pierre Jeannerod, Christophe Mouilleron, David Pfannholzer, and Nathalie Revol. LEMA: Towards a language for reliable arithmetic. In International Workshop on Programming Languages for Mechanized Mathematics Systems (PLMMS 2010), volume 44 of ACM Communications in Computer Algebra, pages 41--52. ACM, June 2010. [ bib | DOI ] |
| [63] | Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. ACM SIGARCH Computer Architecture News, 38:73--79, 2010. [ bib | http | .pdf ] |
| [64] | Florent de Dinechin, Honoré Takeugming, and Jean-Marc Tanguy. A 128-tap complex FIR filter processing 20 giga-samples/s in a single FPGA. In 44th Asilomar Conference on Signals, Systems & Computers, 2010. [ bib | .pdf ] |
| [65] | Florent de Dinechin. A flexible floating-point logarithm for reconfigurable computers. Lip research report rr2010-22, ENS-Lyon, 2010. [ bib | http ] |
| [66] | Florent de Dinechin, Hong Diep Nguyen, and Bogdan Pasca. Pipelined FPGA adders. In Field-Programmable Logic and Applications, pages 422--427, 2010. [ bib | .pdf ] |
| [67] | Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Multiplicative square root algorithms for FPGAs. In Field-Programmable Logic and Applications, pages 574--577, 2010. [ bib | .pdf ] |
| [68] | Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, and Radu Tudoran. Multipliers for floating-point double precision and beyond on FPGAs. In Highly-Efficient Accelerators and Reconfigurable Technologies, 2010. [ bib | .pdf ] |
| [69] | Florent de Dinechin, Mioara Joldes, and Bogdan Pasca. Automatic generation of polynomial-based hardware architectures for function evaluation. In Application-specific Systems, Architectures and Processors. IEEE, 2010. [ bib | .pdf ] |
| [70] | Florent de Dinechin, Mioara Joldes, Bogdan Pasca, and Guillaume Revy. Racines carrées multiplicatives sur FPGA. In SYMPosium en Architectures nouvelles de machines (SYMPA), Toulouse, September 2009. [ bib | .pdf ] |
| [71] | Florent de Dinechin and Bogdan Pasca. Large multipliers with fewer DSP blocks. In Field Programmable Logic and Applications, pages 250--255. IEEE, August 2009. [ bib | .pdf ] |
| [72] | Florent de Dinechin, Cristian Klein, and Bogdan Pasca. Generating high-performance custom floating-point pipelines. In Field Programmable Logic and Applications, pages 59--64. IEEE, August 2009. [ bib | .pdf ] |
| [73] | Jean-Michel Muller, Nicolas Brisebarre, Florent de Dinechin, Claude-Pierre Jeannerod, Vincent Lefèvre, Guillaume Melquiond, Nathalie Revol, Damien Stehlé, and Serge Torres. Handbook of Floating-Point Arithmetic. Birkhauser Boston, 2009. [ bib ] |
| [74] | Florent de Dinechin, Bogdan Pasca, Octavian Creţ, and Radu Tudoran. An FPGA-specific approach to floating-point accumulation and sum-of-products. In Field-Programmable Technologies, pages 33--40. IEEE, 2008. [ bib | .pdf ] |
| [75] | Nicolas Brisebarre, Florent de Dinechin, and Jean-Michel Muller. Integer and floating-point constant multipliers for FPGAs. In Application-specific Systems, Architectures and Processors, pages 239--244. IEEE, 2008. [ bib | .pdf ] |
| [76] | Christoph Lauter and Florent de Dinechin. Optimising polynomials for floating-point implementation. In Real Numbers and Computers, pages 7--16, 2008. [ bib | .pdf ] |
| [77] | Florent de Dinechin, Miloš D. Ercegovac, Jean-Michel Muller, and Nathalie Revol. Encyclopedia of Computer Science and Engineering, chapter Digital Arithmetic. Wiley, 2008. [ bib ] |
| [78] | Jérémie Detrey and Florent de Dinechin. Fonctions élémentaires en virgule flottante pour les accélérateurs reconfigurables. Technique et Science Informatiques, 27(6):673--698, 2008. [ bib ] |
| [79] | N. Brisebarre, F. de Dinechin, and J.-M. Muller. Multiplieurs et diviseurs constants en virgule flottante avec arrondi correct. In RenPar'18, SympA'2008, CFSE'6, 2008. [ bib ] |
| [80] | Ionuţ Trestian, Octavian Creţ, Laura Creţ, Lucia Vǎcariu, Radu Tudoran, and Florent de Dinechin. FPGA-based computation of the inductance of coils used for the magnetic stimulation of the nervous system. In Biomedical Electronics and Devices, volume 1, pages 151--155, 2008. [ bib | .pdf ] |
| [81] | Octavian Creţ, Ionuţ Trestian, Radu Tudoran, Laura Darabant, Lucia Vǎcariu, and Florent de Dinechin. Accelerating the computation of the physical parameters involved in transcranial magnetic stimulation using FPGA devices. Romanian Journal of Information, Science and Technology, 10(4):361--379, 2007. [ bib ] |
| [82] | Florent de Dinechin. Matériel et logiciel pour l'évaluation de fonctions numériques. Précision, performance et validation. PhD thesis, Université Claude Bernard - Lyon 1, 2007. [ bib | .pdf ] |
| [83] | Jérémie Detrey and Florent de Dinechin. Floating-point trigonometric functions for FPGAs. In Field-Programmable Logic and Applications, pages 29--34. IEEE, 2007. [ bib | .pdf ] |
| [84] | Florent de Dinechin, Jérémie Detrey, Octavian Creţ, and Radu Tudoran. When FPGAs are better at floating-point than microprocessors. Technical Report ensl-00174627, ÉNS Lyon, 2007. http://prunel.ccsd.cnrs.fr/ensl-00174627. [ bib ] |
| [85] | Florent de Dinechin, Christoph Quirin Lauter, and Jean-Michel Muller. Fast and correctly rounded logarithms in double-precision. Theoretical Informatics and Applications, 41:85--102, 2007. [ bib | .pdf ] |
| [86] | Jérémie Detrey and Florent de Dinechin. Parameterized floating-point logarithm and exponential functions for FPGAs. Microprocessors and Microsystems, Special Issue on FPGA-based Reconfigurable Computing, 31(8):537--545, 2007. [ bib | DOI | .pdf ] |
| [87] | Jérémie Detrey, Florent de Dinechin, and Xavier Pujol. Return of the hardware floating-point elementary function. In 18th Symposium on Computer Arithmetic, pages 161--168. IEEE, 2007. [ bib | .pdf ] |
| [88] | Jérémie Detrey and Florent de Dinechin. A tool for unbiased comparison between logarithmic and floating-point arithmetic. Journal of VLSI Signal Processing, 49(1):161--175, 2007. [ bib | DOI | .pdf ] |
| [89] | Catherine Daramy-Loirat, David Defour, Florent de Dinechin, Matthieu Gallet, Nicolas Gast, Christoph Lauter, and Jean-Michel Muller. CR-LIBM: A library of correctly rounded elementary functions in double-precision. Research report, LIP, December 2006. https://hal-ens-lyon.archives-ouvertes.fr/ensl-01529804. [ bib | .pdf ] |
| [90] | Jérémie Detrey and Florent de Dinechin. Opérateurs trigonométriques en virgule flottante sur FPGA. In RenPar'17, SympA'2006, CFSE'5 et JC'2006, pages 96--105, Perpignan, France, 2006. [ bib | .pdf ] |
| [91] | Florent de Dinechin. Elementary functions for double-precision interval arithmetic. In Scientific Computing, Computer Arithmetic and Validated Numerics. GAMM - IMACS, 2006. [ bib ] |
| [92] | Florent de Dinechin and Sergey Maidanov. Software techniques for perfect elementary functions in floating-point interval arithmetic. In Real Numbers and Computers, 2006. [ bib | .pdf ] |
| [93] | Caroline Collange, Jérémie Detrey, and Florent de Dinechin. Floating point or LNS: choosing the right arithmetic on an application basis. In 9th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD'2006), pages 197--203, Dubrovnik, Croatia, 2006. IEEE. [ bib | DOI | .pdf ] |
| [94] | Florent de Dinechin, Eric McIntosh, and Franck Schmidt. Massive tracking on heterogeneous platforms. In 9th International Computational Accelerator Physics Conference (ICAP), 2006. [ bib ] |
| [95] | Florent de Dinechin and G. Villard. High precision numerical accuracy in physics research. Nuclear Inst. and Methods in Physics Research, A, 559:207--210, 2006. [ bib ] |
| [96] | Florent de Dinechin, Christoph Lauter, and Guillaume Melquiond. Assisted verification of elementary functions using Gappa. In Proceedings of the 2006 ACM Symposium on Applied Computing, pages 1318--1322, 2006. [ bib ] |
| [97] | Florent de Dinechin, Alexey Ershov, and Nicolas Gast. Towards the post-ultimate libm. In 17th Symposium on Computer Arithmetic, pages 288--295. IEEE, 2005. [ bib | .pdf ] |
| [98] | Jérémie Detrey and Florent de Dinechin. A parameterized floating-point exponential function for FPGAs. In Field-Programmable Technology. IEEE, 2005. [ bib | .pdf ] |
| [99] | Jérémie Detrey and Florent de Dinechin. A parameterizable floating-point logarithm operator for FPGAs. In 39th Asilomar Conference on Signals, Systems & Computers. IEEE, 2005. [ bib | .pdf ] |
| [100] | Jérémie Detrey and Florent de Dinechin. Table-based polynomials for fast hardware function evaluation. In Application-specific Systems, Architectures and Processors, pages 328--333. IEEE, 2005. [ bib | .pdf ] |
| [101] | Florent de Dinechin and Arnaud Tisserand. Multipartite table methods. IEEE Transactions on Computers, 54(3):319--330, 2005. [ bib | .pdf ] |
| [102] | Jérémie Detrey and Florent de Dinechin. Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. Technique et science informatiques, 24(6):625--643, 2005. [ bib ] |
| [103] | Florent de Dinechin, Catherine Loirat, and Jean-Michel Muller. A proven correctly rounded logarithm in double-precision. In RNC6, Real Numbers and Computers, 2004. [ bib ] |
| [104] | Jérémie Detrey and Florent de Dinechin. Second order function approximation using a single multiplication on FPGAs. In 14th Intl Conference on Field-Programmable Logic and Applications (LNCS 3203), pages 221--230. Springer, 2004. [ bib | .pdf ] |
| [105] | Florent de Dinechin, David Defour, and Ch. Q. Lauter. Fast correct rounding of elementary functions in double precision using double-extended arithmetic. Technical Report 2004-10, LIP, École Normale Supérieure de Lyon, 2004. [ bib ] |
| [106] | Florent de Dinechin, Tanguy Risset, Manju Manjunathaiah, and Michael Spivey. System specification and design languages (best of FDL'02). chapter Design of highly parallel architectures with Alpha and Handel. Kluwer, 2003. [ bib ] |
| [107] | Jérémie Detrey and Florent de Dinechin. A VHDL library of LNS operators. In 37th Asilomar Conference on Signals, Systems and Computers, 2003. [ bib ] |
| [108] | Jérémie Detrey and Florent de Dinechin. Outils pour une comparaison sans a priori entre arithmétique logarithmique et arithmétique flottante. In M. Auguin, F. Baude, D. Lavenier, and M. Riveill, editors, Actes de RenPar'15, CFSE'3 et SympAAA'2003, 2003. [ bib ] |
| [109] | David Defour, Catherine Daramy, Florent de Dinechin, and Jean-Michel Muller. CR-LIBM: a correctly rounded elementary function library. In Advanced Signal Processing Algorithms, Architectures, and Implementations, 2003. [ bib ] |
| [110] | Florent de Dinechin and David Defour. Software carry-save: A case study for instruction-level parallelism. In Seventh International Conference on Parallel Computing Technologies, 2003. [ bib | .pdf ] |
| [111] | Florent de Dinechin, Tanguy Risset, Manju Manjunathaiah, and Michael Spivey. Design of highly parallel architectures with Alpha and Handel. In Forum on Design Languages, 2002. [ bib ] |
| [112] | David Defour, Florent de Dinechin, and Jean-Michel Muller. A new scheme for table-based evaluation of functions. In 36th Asilomar Conference on Signals, Systems, and Computers, 2002. [ bib ] |
| [113] | David Defour and Florent de Dinechin. Software carry-save for fast multiple-precision algorithms. In 35th International Congress of Mathematical Software, 2002. [ bib ] |
| [114] | Florent de Dinechin and Jérémie Detrey. Multipartite tables in JBits for the evaluation of functions on FPGAs. In IEEE Reconfigurable Architecture Workshop, International Parallel and Distributed Symposium, 2002. [ bib | .pdf ] |
| [115] | M. Daumas, Florent de Dinechin, and Arnaud Tisserand, editors. Introduction à l'arithmétique des ordinateurs, volume 13, 2001. [ bib ] |
| [116] | David Defour, F. de Dinechin, and Jean-Michel Muller. Correctly rounded exponential function in double precision arithmetic. In Advanced Signal Processing Algorithms, Architectures, and Implementations, 2001. [ bib ] |
| [117] | Florent de Dinechin and Arnaud Tisserand. Some improvements on multipartite table methods. In 15th Symposium on Computer Arithmetic, pages 128--135, 2001. [ bib | .pdf ] |
| [118] | Florent de Dinechin. Le prix du routage dans les FPGAs. Technique et science informatiques, 20(2):229--243, 2001. [ bib ] |
| [119] | Florent de Dinechin and Arnaud Tisserand. Table-based methods comparison for low-precision evaluation of the sine and cosine functions on FPGAs. In Advanced Signal Processing Algorithms, Architectures, and Implementations, 2000. [ bib ] |
| [120] | Florent de Dinechin and Vincent Lefèvre. Constant multipliers for FPGAs. In Parallel and Distributed Processing Techniques and Applications, pages 167--173, 2000. [ bib | .pdf ] |
| [121] | Florent de Dinechin. The price of routing in FPGAs. Journal of Universal Computer Science, 6(2):227--239, 2000. [ bib | .pdf ] |
| [122] | Florent de Dinechin. Le prix du routage dans les FPGAs. In Sympa'5, cinquième symposium en architectures nouvelles de machines, Rennes, France, 1999. [ bib ] |
| [123] | Florent de Dinechin. Towards adaptable hierarchical placement for FPGAs. In FPGA'99, 1999. Also available as INRIA RR-3776 and LIP RR1999-50. [ bib | .ps.gz ] |
| [124] | W. Luk, P. Andreou, A. Derbyshire, F. de Dinechin, J. Rice, N. Shirazi, and D. Siganos. A reconfigurable engine for real-time video processing. In Field Programmable Logic and Applications, pages 169--178, 1998. [ bib ] |
| [125] | Florent de Dinechin. Systèmes structurés d'équations récurrentes : mise en œuvre dans le langage Alpha et applications. thesis, université de Rennes I, 1997. [ bib | .ps.gz ] |
| [126] | Florent de Dinechin, Tanguy Risset, and Sophie Robert. Hierarchical static analysis for improving the complexity of linear algebra algorithms. In Parallel Computing. Elsevier, 1997. [ bib | .pdf ] |
| [127] | Florent de Dinechin. Libraries of schedule-free operators in Alpha. In Application Specific Array Processors. IEEE Computer Society Press, 1997. [ bib | .pdf ] |
| [128] | Florent de Dinechin. Self-replication in a 2D von Neumann architecture. In European Conference on Artificial Life. MIT Press/Bradford Books, 1997. [ bib | .pdf ] |
| [129] | Florent de Dinechin and Patricia Le Moënner. Automatic synthesis of regular architectures optimized at the bit level. In Workshop on Design Methodologies for Signal Processing, 1996. [ bib | .pdf ] |
| [130] | Rumen Andonov, Florent de Dinechin, Sanjay Rajopadhye, and Doran Wilde. A regular VLSI array for an irregular algorithm. In International Workshop on Parallel Algorithms for Irregularly Structured Problems. Springer-Verlag Lecture Notes in Computer Science, 1996. [ bib | .pdf ] |
| [131] | Florent de Dinechin and Sophie Robert. Hierarchical static analysis of structured systems of affine recurrence equations. In Application Specific Array Processors. IEEE, 1996. [ bib | .pdf ] |
| [132] | Florent de Dinechin and Helmut Weberpals. A localized parallel sorting algorithm and its implementation. In ParCo'95, Advances in Parallel Computing. North-Holland, 1996. [ bib ] |
| [133] | Florent de Dinechin, Patrick Quinton, and Tanguy Risset. Structuration of the Alpha language. In Massively Parallel Programming Models, pages 18--24. IEEE, 1995. [ bib | .pdf ] |
| [134] | Helmut Weberpals and Florent de Dinechin. Analysis of parallel algorithms for a shared virtual memory computer. In ParCo'93, Advances in Parallel Computing, pages 719--723. North-Holland, 1994. [ bib ] |
This file was generated by bibtex2html 1.99.