HiPEAC 2013 Tutorial

Building Custom Arithmetic Operators

with the FloPoCo Generator

This tutorial will take place Tuesday 22/01/2013 during HiPEAC 2013 in Berlin. Do not hesitate to contact me for more information.

You may download here preliminary slides as well as tutorial files in a tgz archive.

Custom hardware arithmetic components are an opportunity to improve the efficiency of both ASIC and FPGA applications.

- Operators may be specialized for a context: application-specific precision, constant inputs, etc.
- Several operators may be fused into a single optimized architecture. For instance, computing x²+y²+z² requires squarers, which are simpler than multipliers, and adders of positive values, which in floating-point are simpler than standard adders.
- Specific architectures may be designed for operators that are typically implemented as software, such as elementary functions: exp, log, sin, cos, ...
- Some applications require exotic arithmetic (cryptography, logarithmic number system, decimal...).
- The performance of an operator may be tuned to the needs of its context through pipelining, memory/computation tradeoff, etc.
- etc.

However, designing custom operators has a cost, which may be a one-time cost if the operator is application-specific. The open-source FloPoCo core generator attempts to address this issue. Follow this link for many more examples of custom operators.

From a user point of view, FloPoCo is a command-line tool that inputs operator specifications and outputs high-quality synthesizable VHDL. FloPoCo offers more than 50 operators in fixed or floating point, each parameterized in precision, but also in target frequency. Some of these operators are actually open-ended meta-operator, for instance there are universal function approximators, and multipliers by arbitrary constants. The numerical quality of all these operators is well specified.

But FloPoCo is also an open C++ framework for developing new custom operators with high productivity. In particular, FloPoCo generates test benches from a very short mathematical description of the expected functionality of an operator. It also manages the generation of correct-by-construction pipelines, so a designer may focus on the combinatorial function. Finally, FloPoCo already offers most of the building blocks needed for complex custom operators.

This tutorial will cover the two aspects of FloPoCo presented above. It will first briefly survey the operators available in the current version of FloPoCo, then concentrate on designing a new operator using the framework.

This tutorial is intended for

- ASIC or FPGA designers with a need of custom arithmetic
- developers of High-Level Synthesis tools wishing to enhance HLS tools with richer custom arithmetic capabilities
- designers of high-performance compute kernels (filters, transforms) wishing to optimize their arithmetic components
- anybody wishing to learn about custom arithmetic

FloPoCo is a generator of VHDL written in C++: a basic knowledge of these two languages will be helpful.

It is recommended to come with a laptop with FloPoCo version 2.4.0 installed, as instructed here.